Principle & Implementation

: SiGe-Chip (2mm x 2mm)

♦ MLBS Generator

♦ Example:
Clock rate 9 GHz
9 stage shift register

: Signal spectrum

Digital UWB Correlator
(multi-channel arrangement)

Time resolution:

Usable bandwidth:

♦ Technical Data

• Customer IC: 0,8 mm Si/SiGe HBT	• 9 stage shift register
• max. clock rate 12 GHz	• 128 ... 1024 binary divider
• differential RF-ports (100 W)	• clock line cascading
• TTL-control ports	• overall jitter: not detectable (< 140 fs)
• max. dynamic: 100 dB

: RF-chips mounted on LTCC The differential lines are well visible.

♦ RF-part

Transmitter
                Output power: 5 dBm
                Rise/fall time: 40 ps
      T&H
                Sampling rate: 5 MHz ... 5 GHz
                Bandwidth: 6,5 GHz
                Effective number of bits: 6 bit
                CP1dB: -5 dBm
                IP3: 10 dBm
      Mounting
                Flip-Chip
                4 layer LTCC